Verilog
The Verilog HDL is a hardware description language, used for the design of ASICs and FPGAs. Verilog has a syntax reminiscent of C, which helps explain its rapid take up among engineers who had already learnt to use that language. It is case-sensitive.
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2 Example |
History
Beginning
Verilog was first developed at Gateway Design Automation around 1984 as a hardware modeling language. Gateway Design Automation was later purchased by Cadence Design Systems in 1990. Cadence now had full proprietary rights to Gateway's Verilog and the Verilog-XL simulator logic simulators.
Standard Opened
With the increasing success of VHDL, Cadence moved down the Open Standards route. Cadence transfered Verilog into the public domain under the Open Verilog International (OVI) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.
Verilog 2001
Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became IEEE Standard 1364-2001 known as Verilog 2001
An example counter circuit follows:
//enable CEP is a clock enable only
//enable CET is a clock enable and enables the TC output
//a counter using the Verilog language
input rst;
input clk;
input cet;
input cep;
output [size-1:0] count;
output tc;
reg [size-1:0] count;
wire tc;
always @ (posedge rst or posedge clk)
begin
if (rst)
count = 5'b0;
else if (cet && cep)
begin
if (count == length-1)
begin
count = 5'b0;
end
else
count = count + 1;
end
end
assign tc = (cet && (count == length-1));
Example
module Div20x (rst, clk, cet, cep, count,tc);
//TITLE 'Divide-by-20 Counter with enables'
parameter size = 5;
parameter length = 20;
endmodule
